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VFD Driver/Controller IC
PT6313-S
DESCRIPTION
PT6313-S is a Vacuum Fluorescent Display (VFD) Controller driven on a 1/4 to 1/8 duty factor. Eight segment output lines, 4 grid output lines, 4 segment/grid output drive lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip micro computer. Serial data is fed to PT6313-S via a three-line serial interface. It is housed in a 28pins, SOP.
FEATURES
* * * * * * * * CMOS Technology Low Power Consumption Key Scanning (8 x 2 matrix) Multiple Display Modes: (8 Segments, 8 Digits to 12 Segments, 4 Digits) 8-Step Dimming Circuitry Serial Interface for Clock, Data Input, Data Output, Strobe Pins No External Resistors Needed for Driver Outputs Available in 28pins, SOP
APPLICATION
* Microcomputer Peripheral Devices
PT6313-S V1.2
-1-
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
BLOCK DIAGRAM
SG1/KS1 Control DIN DOUT CLK STB Serial Data Interface Segment Driver/ Display Memory Grid Driver/ Key Scan Output OSC OSC R SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7 SG8/KS8 SG9/GR8 SG10/GR7 Timing Generator SG11/GR6 SG12/GR5
Key Matrix Memory
GR1 Grid Driver GR2 GR3 GR4
Dimming Circuit
K1
K2
VDD
GND
VEE
PT6313-S V1.2
-2-
September, 2005
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VFD Driver/Controller IC
PT6313-S
PIN CONFIGURATION
CLK STB K1 K2 VSS VDD SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7 SG8/KS8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23
DIN DOUT OSC VSS VDD GR1 GR2 GR3 GR4 SG12/GR5 SG11/GR6 SG10/GR7 SG9/GR8 VEE
P T 63 1 3- S
22 21 20 19 18 17 16 15
PT6313-S V1.2
-3-
September, 2005
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VFD Driver/Controller IC
PT6313-S
PIN DESCRIPTION
Pin Name
CLK
I/O
I
Description
Clock Input Pin This pin reads serial data at the rising edge and outputs data at the falling edge. Serial Interface Strobe Pin The data input after the STB has fallen is processed as a command. When this in is "HIGH", CLK is ignored. Key Data Input Pins The data inputted to these pins is latched at the end of the display cycle. Logic Ground Pin Logic Power Supply High-Voltage Segment Output Pins Also acts as the Key Source. Pull-Down Level High-Voltage Segment Output Pins High-Voltage Grid Output Pins Oscillator Input Pin A resistor is connected to this pin to determine the oscillation frequency. Data Output Pin (N-Channel, Open-Drain) This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit). Data Input Pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit).
Pin No.
1
STB
I
2
K1 to K2 VSS VDD SG1/KS1 to SG8/KS8 VEE SG9/GR8 to SG12/GR5 GR4 to GR1 OSC
I O O O I
3, 4 5, 25 6, 24 7 to 14 15 16 to 19 20 to 23 26
DOUT
O
27
DIN
I
28
PT6313-S V1.2
-4-
September, 2005
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VFD Driver/Controller IC
PT6313-S
FUNCTION DESCRIPTION
COMMANDS
Commands determine the display mode and status of PT6313-S. A command is the first byte (b0 to b7) inputted to PT6313-S via the DIN Pin after STB Pin has changed from "HIGH" to "LOW" State. If for some reason the STB Pin is set to "HIGH" while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid.
COMMAND 1: DISPLAY MODE SETTING COMMANDS
PT6313-S provides 4 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6313-S via the DIN Pin when STB is "LOW". However, for these commands, the bits 4 to 6 (b3 to b5) are ignored, bits 7 & 8 (b6 to b7) are given a value of "0". The Display Mode Setting Commands determine the number of segments and grids to be used (1/4 to 1/8 duty, 12 to 8 segments). When Power is turned "ON", the 8-digit, 8-segment mode is selected. MSB 0 0 LSB b2 b1 b0 Display Mode Settings: 000: 4 digits, 12 segments 001: 5 digits, 11 segments 010: 6 digits, 10 segments 011: 7 digits, 9 segments 100: 8 digits, 8 segments
Not Relevant
PT6313-S V1.2
-5-
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
Display Mode and RAM Address Data transmitted from an external device to PT6313-S via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6313-S are given below in 8 bits unit.
SG1 SG4 00HL 02HL 04HL 06HL 08HL 0AHL 0CHL 0EHL b0 xxHL Lower 4 bits b3 b4 xxHU Higher 4 bits b7 SG5 SG8 00HU 02HU 04HU 06HU 08HU 0AHU 0CHU 0EHU SG9 SG12 01HL 03HL 05HL 07HL 09HL 0BHL 0DHL 0FHL DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8
PT6313-S V1.2
-6-
September, 2005
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VFD Driver/Controller IC COMMAND 2: DATA SETTING COMMANDS
PT6313-S
The Data Setting Commands executes the Data Write or Data Read Modes for PT6313-S. The Data Setting Command, the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of "1" while bit 8 (b7) is given the value of "0". Please refer to the diagram below. When power is turned ON, the bit 4 to bit 1 (b3 to b0) are given the value of "0". MSB 0 1 LSB b3 b2 b1 b0 Data Write & Read Mode Settings: 00: Write Data to Display Mode 10: Read Key Data Address Increment Mode Settings (Display Mode): 0: Increment Address after Data has been Written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode
Not Relevant
PT6313-S V1.2
-7-
September, 2005
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VFD Driver/Controller IC
PT6313-S Key Matrix & Key Input Data Storage RAM PT6313-S Key Matrix consists of 8 x 2 array as shown below:
K1 K2
PT6313-S
SG 1 /KS1
SG 2 /KS2
SG 3 /KS3
SG 4 /KS4
SG 6 /KS6
SG 5 /KS5
SG 7 /KS7
Each data inputted by each key are stored as follows. They are read by a READ Command, starting from the last significant bit. When the most significant bit of the data (SG8, b7) has been read, the least significant bit of the next data (SG1, b0) is read. K1............K1 SG1/KS1 SG5/KS5 b0.............b1 K2............K3 K4............K5 K6...............K7 SG2/KS2 SG3/KS3 SG4/KS4 SG6/KS6 SG7/KS7 SG8/KS8 b2.............b3 b4.............b5 b6................b7 Reading Sequence
PT6313-S V1.2
-8-
SG 8 /KS8
September, 2005
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VFD Driver/Controller IC COMMAND 3: ADDRESS SETTING COMMANDS
PT6313-S
Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of "00H" to "0FH". If the address is set to 10H or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at "00H". Please refer to the diagram below. MSB 1 1 0 0 LSB b3 b2 b1 b0 Address: 00H to 0FH
COMMAND 4: DISPLAY CONTROL COMMANDS
The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF. MSB 1 0 LSB b3 b2 b1 b0 Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width - 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off 1: Display On
Not Relevant
PT6313-S V1.2
-9-
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
SCANNING AND DISPLAY TIMING
The Key Scanning and display timing diagram is given below. The data of the 8 x 2 matrix is stored in the RAM.
T DISPLAY =500 s Key Scan Data
SG Output G1
DIG1
DIG2
DIG3
DIGn
12
8
DIG1
G2 G3
Gn 1 Frame = T DISPLAY X (n +1)
PT6313-S V1.2
- 10 -
September, 2005
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VFD Driver/Controller IC
PT6313-S
SERIAL COMMUNICATION FORMAT
The following diagram shows the PT6313-S serial communication format. The DOUT Pin is an N-channel, open-drain output pin; therefore, it is highly recommended that an external pull-up resistor (1K to 10K) must be connected to DOUT.
Reception (Data/Command Write)
If data continues STB
DIN
b0
b1
b2
b6
b7
CLK
1
2
3
7
8
Transmission (Data Read)
STB DIN CLK b0 1 b1 2 b2 3 b3 4 b4 5 b5 6 b6 7 b7 8
t wait
1
2
3
4
5
6
DOUT Data Read Command is set
b0
b1
b2
b3
b4
b5
Data Reading Starts
where: twait (waiting time) > 1s It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1s.
PT6313-S V1.2
- 11 -
September, 2005
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VFD Driver/Controller IC
PT6313-S
SWITCHING CHARACTERISTIC WAVEFORM
PT6313-S Switching Characteristics Waveform is given below.
fosc OSC
50 %
PW ST B ST B PW CL K CLK tsetup DIN tPZL DOUT tTHZ Sn/Gn
90 % 10 %
PW CL K
tCL K- ST B
tho ld
tPLZ
tTZH
where: PW CLK (Clock Pulse Width) 400ns PW STB (Strobe Pulse Width) 1s t setup (Data Setup Time) 100ns thold (Data Hold Time) 100ns tCLK-STB (Clock - Strobe Time) 1s tTHZ (Fall Time) 150s tTZH (Grid Rise Time) 0.5s (VDD=5V) t PZL (Propagation Delay Time) 100ns tTZH (Grid Rise Time) 1.0s (VDD=3.3V) tPLZ (Propagation Delay Time) 400ns tTZH (Segment Rise Time) 2.0s (VDD=5V) tTZH (Segment Rise Time) 3.0s (VDD=3.3V) fosc=Oscillation Frequency
PT6313-S V1.2
- 12 -
September, 2005
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VFD Driver/Controller IC
PT6313-S
APPLICATIONS
Display memory is updated by incrementing addresses. Please refer to the following diagram.
ST B
CLK DIN
Co mm and 2 Co mm and 3 Da ta 1 Da ta n Co mm and 1 Co mm and 4
where: Command 1: Display Mode Setting Command Command 2: Data Setting Command Command 3: Address Setting Command Data 1 to n: Transfer Display Data (16 Bytes max.) Command 4: Display Control Command The following diagram shows the waveforms when updating specific addresses.
ST B CLK DIN
Co mm and 2 Co mm and 3 Da ta Co mm and 3 Da ta
where: Command 2: Data Setting Command Command 3: Address Setting Command Data: Display Data
PT6313-S V1.2
- 13 -
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
RECOMMENDED SOFTWARE FLOWCHART
START Delay 200 ms
SET COMMAND 2 (Write Data)
SET COMMAND 3 Clear Display RAM (See Note 5)
INITIAL SETTING
SET COMMAND 1
SET COMMAND 4 (88H~8FH: Display ON)
MAIN PROGRAM
SET COMMAND 2 (Read Key & Write Data Included) MAIN LOOP SET COMMAND 3
SET COMMAND 1
SET COMMAND 4
END
Note: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting.
PT6313-S V1.2 - 14 September, 2005
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VFD Driver/Controller IC
PT6313-S
ABSOLUTE MAXIMUM RATINGS
(Unless otherwise stated, Ta=25, GND=0V) Parameter Symbol Logic Supply Voltage VDD Driver Supply Voltage VEE Logic Input Voltage VI VFD Driver Output Voltage VO VFD Driver Output Current Operating Temperature Storage Temperature IOVFD Topr Tstg
Ratings -0.5 to +7 VDD +0.5 to VDD -40 -0.5 to VDD +0.5 VEE -0.5 to VDD +0.5 -40 (Grid) -15 (Segment) -40 to +85 -65 to +150
Unit V V V V
mA

RECOMMENDED OPERATING RANGE
(Unless otherwise stated, Ta=-25, GND=0V)
Parameter
Logic Supply Voltage High-Level Input Voltage Low-Level Input Voltage Driver Supply Voltage
Symbol
VDD VIH VIL VEE
Min. 3.0 0.7VDD 0 VDD -35
Ratings Typ. 5 -
Max. 5.5 VDD 0.3VDD 0
Unit
V V V V
PT6313-S V1.2
- 15 -
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, VDD=5V, GND=0V, VEE=VDD-35 V, Ta=25) Parameter Symbol Test Condition Min. Typ. Max. Unit DOUT, 0.4 V Low-Level Output Voltage VOLDOUT IOLDOUT=4mA VO=VDD -2V -3 mA High-Level Output Current IOHSG SG1/KS1 to SG8/KS8 VO=VDD -2V High-Level Output Current IOHGR GR1 to GR4, -15 mA SG9/GR8 to SG12/GR5 High-Level Input Voltage VIH 0.7VDD VDD V Low-Level Input Voltage VIL 0.3VDD V Oscillation Frequency fosc R=68K 350 500 650 KHz Input Current II VI=VDD or VSS 1 A Dynamic Current IDDdyn Under no load Display OFF 5 mA Consumption
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, VDD=3.3V, GND=0V, VEE=VDD-35 V, Ta=25) Parameter Symbol Test Condition Min. Typ. Max. Unit DOUT, 0.4 V Low-Level Output Voltage VOLDOUT IOLDOUT=4mA VO=VDD -2V -1.5 mA High-Level Output Current IOHSG SG1/KS1 to SG8/KS8 VO=VDD -2V High-Level Output Current IOHGR GR1 to GR4, -6 mA SG9/GR8 to SG12/GR5 High-Level Input Voltage VIH 0.7VDD VDD V Low-Level Input Voltage VIL 0.3VDD V Oscillation Frequency fosc R=68K 350 500 650 KHz Input Current II VI=VDD or VSS 1 A Dynamic Current IDDdyn Under no load Display OFF 3 mA Consumption
PT6313-S V1.2
- 16 -
September, 2005
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VFD Driver/Controller IC
PT6313-S
APPLICATION CIRCUIT
VDD 10K
MCU
VDD
10 K 10 K
CLK STB K1 K2 VSS VDD SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7 SG8/KS8
DIN DOUT OSC VSS VDD GR1 GR2 GR3 GR4 SG12/GR5 SG11/GR6 SG10/GR7 SG9/GR8 VEE
68 K
0.1 F
VDD
G8 G 7 G6 G5 G 4 G3 G2 G1
8-GRID x 8-SEGMENT VFD
S8 S7 S6 S5 S 4 S3 S2 S1
VEE
10K
1N4148 x 8
10K
Note: The capacitor (0.1F) connected between the GND and the VDD pins must be located as close as possible to the PT6313-S chip.
PT6313-S V1.2
- 17 -
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
ORDER INFORMATION
Valid Part Number PT6313-S PT6313-S (L) Package Type 28pins, SOP, 300mil 28pins, SOP, 300mil Top Code PT6313-S PT6313-S
Notes: 1. (L), (C) or (S) = Lead Free. 2. The Lead Free mark is put in front of the date code.
PT6313-S V1.2
- 18 -
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
PACKAGE INFORMATION
28 PINS, SOP, 300 MIL
Symbol A A1 B C D E e H h L
Min. 2.35 0.10 0.33 0.23 17.70 7.40
1.27 bsc. 10.00 0.25 0.40 0o
Max 2.65 0.30 0.51 0.32 18.10 7.60
10.65 0.75 1.27 8o
PT6313-S V1.2
- 19 -
September, 2005
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6313-S
Notes: 1. Dimensioning and tolerancing per ANSI Y14.5-1982. 2. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006 in) per side. 3. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusion shall not exceed 0.15mm (0.016in) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. L is the length of terminal for soldering to a substrate. 6. N is the number of terminal positions (N=28). 7. The lead width B as measured 0.36mm (0.014in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024 in). 8. Controlling dimension: MILLIMETER 9. Refer to JEDEC MS-013 Variation AE. JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
PT6313-S V1.2
- 20 -
September, 2005

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